Generally, a power-up signal is used in a semiconductor memory to determine if the level of a power supply voltage VDD reaches a voltage level required for the normal operation of the semiconductor memory when the power supply voltage VDD is applied to the semiconductor memory in an initial stage of the operation thereof.
The power-up signal is necessary because the semiconductor memory may abnormally operate when power is applied to the semiconductor memory before the level of the power supply voltage reaches the voltage level for the normal operation of the semiconductor memory. At this time, if the power-up signal is activated, the power-up signal may become a high level or a low level. In the following description, it is assumed that the power-up signal is a high level.
Accordingly, the semiconductor memory essentially includes a power-up generator that generates a power-up signal activated according to the level of the power supply voltage.
FIG. 1 is a graph for explaining a power-up signal according to the conventional technology.
As shown in FIG. 1, the power-up signal rises corresponding to the level of the power supply voltage VDD when the power supply voltage VDD is applied to the semiconductor memory in an initial stage of the operation thereof. Thereafter, if the level of the power supply voltage VDD exceeds a predetermined voltage level, the power-up signal is low.
Such a power-up signal shorts an internal voltage to the power supply voltage VDD, and resets registers of a logic module for the duration in which the power-up signal PWRUP is high. At this time, if the power-up signal PWRUP is set to a low level, internal voltages are generated from their respective internal voltage drivers, and the logic module becomes a stand-by state, such that the logic module can always be operated.
However, if the power-up signal PWRUP becomes a high level in the lowest level of the power supply voltage VDD due to the requirement for low power supply voltage in a mobile product, registers in all logic modules are reset, so that the level of the power supply voltage VDD of an internal voltage supplying circuit cannot but descend.
Due to such a problem, a driver for an internal voltage must maintain a target voltage level in a low power supply voltage. In other words, since the internal voltage must be applied in the low power supply voltage as soon as the power-up operation is completed, the internal voltage is unstable, so that fatal errors may occur.